1. Field of the Invention
The present invention relates to a charge/discharge control circuit for detecting a voltage and an abnormality of a secondary battery and to a battery device including the charge/discharge control circuit, and more particularly, to a charge/discharge control circuit, which is powered down in response to a signal input from an external terminal and to a battery device including the charge/discharge control circuit.
2. Description of the Related Art
FIG. 3 illustrates a circuit diagram of a battery device including a conventional charge/discharge control circuit. The battery device including the conventional charge/discharge control circuit includes secondary batteries 1 to 4 (such as lithium ion secondary battery cells), a charge control transistor 14 and a discharge control transistor 16 each formed of an FET or the like, a charge/discharge control circuit 22, a microcomputer 21, and external terminals EB+ and EB−.
In the secondary batteries 1 to 4, a positive terminal of the secondary battery 1 is connected to the discharge control transistor 16, and a negative terminal of the secondary battery 4 is connected to the external terminal EB−. The discharge control transistor 16 and the charge control transistor 14 are connected in series. The charge control transistor 14 is connected to the external terminal EB+.
The charge control transistor 14 is a switch element for controlling charge to the secondary batteries 1 to 4 from a charger 20. The discharge control transistor 16 is a switch element for controlling discharge from the secondary batteries 1 to 4 to a load 19. When the charge/discharge control circuit 22 inhibits the charge to the secondary batteries 1 to 4, the charge/discharge control circuit 22 turns OFF the charge control transistor 14. When the charge/discharge control circuit 22 inhibits the discharge from the secondary batteries 1 to 4, the charge/discharge control circuit 22 turns OFF the discharge control transistor 16.
When a charge inhibition signal is input to a CTL terminal 13, the charge/discharge control circuit 22 turns OFF the charge control transistor 14 and turns ON the discharge control transistor 16. Then, even when the charge inhibition signal is input to the CTL terminal 13, if a VMP terminal 12 has an overcurrent detection voltage, the charge/discharge control circuit 22 cancels the charge inhibition signal of the CTL terminal 13.
In this way, in the case where the load 19 is connected between the external terminal EB+ and the external terminal EB−, even when the charge inhibition signal is input from the CTL terminal 13, both the charge control transistor 14 and the discharge control transistor 16 are not turned OFF, and hence it is possible to prevent a lock mode in which a voltage cannot be supplied to the load 19 (see, for example, Japanese Patent Application Laid-open No. 2002-320324 (FIG. 1)).
However, the conventional technology has a problem in that, when a charge inhibition signal is input from the CTL terminal 13 in order to prevent power consumption of the secondary battery at the time of shipment of the battery device, if a load is connected between the external terminal EB+ and the external terminal EB−, a discharge current flows via a parasitic diode 15, resulting in power consumption of the secondary battery. Further, the conventional technology has another problem of power consumption of the charge/discharge control circuit 22.